ClearSpeed Technology, a provider of low-power chip-based systems, has unveiled the CS301 processor, a multithreaded chip designed to improve performance and reduce power consumption for floating-point applications. According to ClearSpeed, the new chip can provide more than twice the processing speed of competing floating-point processors.
“With conventional processor design, increasing performance has tended to come with real penalties in power consumption and heat dissipation, to the point where computing cannot keep up with the demands of today’s emerging applications and rapidly increasing volumes of data,” said Tom Beese, CEO of ClearSpeed Technology.
The CS301 is designed specifically to meet those needs with high performance, power efficiency and “full programmability in C” combined into a single chip, said Beese. “The CS301 is the first in a family of ClearSpeed microprocessors that we believe will challenge present-day thinking by creating a world where scientists, bioinformaticians, engineers and content creators alike can have access to high performance computing anywhere, anytime.”
The CS301 is based on a multithreaded array-processing architecture and includes 64 processing elements, 384 kilobytes of on-chip SRAM and in-out ports interconnecting through ClearSpeed’s ClearConnect bus — a packet-switched bus that supports multiple concurrent transfers.
Each processing element has its own floating-point unit, local memory and in-out capability, making the CS301 suited, according to ClearSpeed, for applications that have high-processing or high-bandwidth requirements.
The company hopes to make inroads into fields that rely on complex mathematically based applications, such as computational biology, digital content creation, nanotechnology development, scientific research and financial modeling.
“We are gratified to see the immediate high level of interest displayed by OEMs in the overall system improvements enabled by the CS301,” said Mike Calise, president of ClearSpeed U.S.
“The dual benefit of performance and efficiency is empowering companies to accelerate existing applications as well as inspiring them to explore new applications that were previously inaccessible,” said Calise.
Coprocessor or Stand-Alone
The CS301 can serve either as a coprocessor alongside an Intel or AMD CPU within a high-performance workstation, blade server or cluster configuration, or as a stand-alone processor for embedded DSP applications like radar pulse compression or image processing.
In applications in which the CS301 is acting as a coprocessor, dynamic libraries offload an application’s inner loops to the CS301. Although these inner loops make up only a small portion of the source code, they are responsible for the majority of the application’s running time.
By offloading the inner loops, the CS301 can — according to ClearSpeed — bypass the traditional bottleneck caused by a CPU’s limited mathematical capability, executing the core of the application more quickly than the main processor.
“To deliver such high levels of performance with full programmability and outstanding gains in power efficiency is a very significant achievement,” said Chris Piercy, president and chairman of the Northern California Nanotechnology Initiative.
“We believe this technology will accelerate the development of nanotechnology and its applications across various industries by making high performance computing more accessible and scalable than ever before,” he added.
The ClearSpeed CS301 is fully programmable in high-level languages, and its software development kit is available now with a C compiler, graphical debugger and suite of supporting tools and libraries.
Focused on delivering high-performance, low-power systems for the computing and communications industries, ClearSpeed’s multithreaded array processing technology is designed to provide customers with the ability to accelerate data-intensive applications at low power.